The manufacturing techniques of semiconductor devices have been gradually advancing. As such, integrated circuits have been proportionally affected.
The internal circuitry of an integrated circuit often operates at different power source voltages (e.g., 3V and 5V). FIG. 1 is a schematic diagram of a conventional CMOS level shift circuit for an integrated circuit. The CMOS level shift circuit generally includes an inverter circuit having a PMOS transistor PM1 and an NMOS transistor NM1. The PMOS transistor PM1 has a source coupled to a power source voltage V.sub.CC2 (e.g., 5V), a drain coupled to an output terminal 30, and a gate coupled to an input terminal 10. The NMOS transistor NM1 has a drain coupled to the output terminal 10, a source coupled to a ground voltage V.sub.SS. (e.g., 0V), and a gate coupled to the input terminal 10. The gates of the PMOS transistor PM1 and the NMOS transistor NM1 are coupled to each other. Here, the power source voltage V.sub.CC2 is an operating voltage of the internal circuitry of the integrated circuit.
When the low voltage (e.g., 0V) is input to the input terminal 10, the low voltage is applied to the gate of the PMOS transistor PM1 and the NMOS transistor NM1. Accordingly, the PMOS transistor PM1 is on and the NMOS transistor NM1 is off, so that the power source voltage V.sub.CC2 is applied to the output terminal 30 through the PMOS transistor PM1.
On the other hand, when the high voltage (e.g., 3V) is input to the input terminal 10, the high voltage is applied to the gate of the PMOS transistor PM1 and the NMOS transistor NM1. Thus, the NMOS transistor NM1 is on, and the PMOS transistor PM1 is weakly on in a static state due to a voltage difference between the gate voltage (e.g., 3V) of the PMOS transistor PM1 and the power source voltage V.sub.CC2 (e.g. 5V). Therefore, a current path is formed between the power source voltage V.sub.CC2 and the ground voltage V.sub.SS, so that a leakage current flows into the inverter circuit via the undesired current path of the PMOS transistor PM1.
Accordingly, there is a problem in the conventional CMOS level shift circuit shown above in that power consumption of the conventional CMOS level shift circuit may occur when the high voltage (e.g., 3V) is input to the input terminal 10. As the voltage difference between the gate voltage (e.g., 3V) of the PMOS transistor and the power source voltage V.sub.CC2 (e.g., 5V) is increased in the static state, the power consumption also increases in proportion thereto.